Applications of Boolean Satisfiability to Verification and Testing of Switch-Level Circuits

This work extends to the switch level the verification and testing techniques based upon boolean satisfiability (SAT), so that SAT-based methodologies can be applied to circuits that cannot be well described at the gate level. The main achieved goal was to define a boolean model describing switch-level circuit operations as a SAT problem instance, to be applied to combinational equivalence checking and bridging-fault test generation. Results are provided for a set of combinational CMOS circuits, showing the feasibility of SAT-based verification and testing of switch-level circuits

Boolean and Pseudo-Boolean Test Generation for Feedback Bridging Faults

Download Citation Email Print Request Permissions Feedback bridging faults may give rise to oscillations within integrated circuits. This work mainly investigates the propagation of oscillations, a behavior that may have a relevant impact on the fault detection. We propose both a logic-level model of the faulty circuit and two techniques aiming to the generation of high-quality test sequences

Bridging fault modeling and simulation for deep submicron CMOS ICs

Testing bridging faults in deep submicron CMOS digital ICs faces new problems because of pushing the technology limits. The growing dispersion of process parameters makes it hard to use conventional bridging fault models for high-quality testing. A new fault model is proposed to account for bridging faults in a way that is independent of electrical parameters and provides a significant coverage metric. Conditions are defined to ensure that (under steady-state conditions) either a fault is detected by a test sequence or it will not give rise to errors for any other input, independently of the actual values of IC parameters. Such a fault model has been implemented in a simulator and validated over combinational benchmarks

Boolean and pseudo-boolean test generation for feedback bridging faults

Feedback bridging faults may give rise to oscillations within integrated circuits. This work mainly investigates the propagation of oscillations, a behavior that may have a relevant impact on the fault detection.We propose both a logic-level model of the faulty circuit and two techniques aiming to the generation of high-quality test sequences

Testing Resistive Opens and Bridging Faults Through Pulse Propagation

Abstract This paper addresses the problems related to resistive opens and bridging faults that lie out of the most critical paths. These faults cannot be detected by traditional delay fault testing because the induced delay defects are not large enough to result in timing violations when the test rate is equal to the nominal operating frequency. In spite of this problem, resistive opens and bridgings should be detected because they may give rise to reliability problems. To detect them, we propose a testing method that is based on the propagation of pulses within the faulty circuit and that exploits the degraded capability of faulty paths to propagate pulses. The effectiveness of our method is analyzed at the transistor level and compared with the use of reduced clock periods to detect the same class of faults. Results show similar performance in the case of resistive opens and better performance in the case of bridgings. Moreover, the proposed approach is not affected by possible problems in the clock distribution